The present disclosure relates to a memory element and a memory device that have a plurality of magnetic layers and make a record using a spin torque magnetization inversion.
Along with a rapid development of various information apparatuses from mobile terminals to large capacity servers, further high performance improvements such as higher integration, increases in a speed, and lower power consumption have been pursued in elements such as a memory element and a logic element. Particularly, semiconductor non-volatile memory has significantly progressed, and, as a large capacity file memory, flash memory has been spreading, and driving out had disk drives with momentum. Meanwhile, looking at development of code storage or working memory, the development of FeRAM (Ferroelectric Random Access Memory), MRAM (Magnetic Random Access Memory), PCRAM (Phase-Change Random Access Memory), or the like has progressed as a substitute for the current NOR flash memory, DRAM or the like in general use. A part of these is already practical in use.
Among them, the MRAM performs the data storage using the magnetization direction of a magnetic body, such that high speed and nearly unlimited (1015 times or more) rewriting can be made, and therefore the MRAM already has been used in fields such as industrial automation and an airplane. Due to high-speed operation and reliability, the MRAM has been expected to be expanded to code storage or working memory in the near future, but in practice, has challenges related to lowering power consumption and increasing capacity. This is a basic problem caused by the recording principle of MRAM, that is, the method of reversing the magnetization using a current magnetic field generated from an interconnect.
As a method of solving this problem, a recording method not utilizing the current magnetic field, that is, a magnetization inversion method is under review. Particularly, research on a spin torque magnetization inversion has been actively made (for example, refer to Japanese Unexamined Patent Application Publication Nos. 2003-17782 and 2008-227388, a specification of U.S. Pat. No. 6,256,223, Phys. Rev. B, 54, 9353 (1996), and J. Magn. Mat., 159, L1 (1996)).
The memory element of a spin torque magnetization inversion is frequently configured using a MTJ (Magnetic Tunnel Junction) in the same way as MRAM.
This configuration uses a phenomenon when spin-polarized electrons passing through a magnetic layer which is fixed in an arbitrary direction enter another free (the direction is not fixed) magnetic layer, the spin-polarized electrons apply a torque to the free magnetic layer (this is also called a spin transfer torque), and when a current of an arbitrary threshold or more flows, the free magnetic layer is inverted. The rewriting of 0/1 is performed by changing the polarity of the current.
An absolute value of a current for this inversion is 1 mA or less in the case of an element with a scale of approximately 0.1 μm. In addition, this current value decreases in proportion to an element volume, such that scaling is possible. In addition, a word line necessary for the generation of a recording current magnetic field in the MRAM is not necessary, such that there is an advantage in that a cell structure becomes simple.
Hereinafter, the MRAM utilizing spin torque magnetization inversion is referred to as an ST-MRAM (Spin Torque-Magnetic Random Access Memory). Spin torque magnetization inversion may be referred to as a spin injection magnetization inversion. Great expectations are put on the ST-MRAM as a non-volatile memory capable of realizing lower power-consumption and larger capacity while maintaining the merits of the MRAM in that high speed and nearly unlimited rewriting may be performed.
FIGS. 6 and 7 show schematic diagrams of the ST-MRAM. FIG. 6 is a perspective view and FIG. 7 is a cross-sectional view.
A drain region 58, a source region 57, and a gate electrode 51 that make up a selection transistor for the selection of each memory cell are formed, respectively, in a semiconductor substrate 60, such as a silicon substrate, at portions isolated by an element isolation layer 52. Among them, the gate electrode 51 also functions as a word line extending in the front-back direction in FIG. 7.
The drain region 58 is formed commonly to left and right selection transistors in FIG. 7, and an interconnect 59 is connected to the drain region 58.
A memory element 53 having a memory layer in which a magnetization direction is inverted by spin torque magnetization inversion is disposed between the source region 57 and bit lines 56 that are disposed at an upper side and extend in the left-right direction in FIG. 6.
This memory element 53 is configured by, for example, a magnetic tunnel junction element (MTJ element). The memory element 53 has two magnetic layers 61 and 62. In the two magnetic layers 61 and 62, one side magnetic layer is set as a magnetization-fixed layer in which the magnetization direction is fixed, and the other side magnetic layer is set as a magnetization-free layer in which that magnetization direction varies, that is, a memory layer.
In addition, the memory element 53 is connected to each bit line 56 and the source region 57 through the upper and lower contact layers 54, respectively. In this manner, when a current is made to flow to the memory element 53, the magnetization direction of the memory layer may be inverted by spin injection.